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arria v device overview 2013.05.06 a v-51001 the arria ? v device family consists of the most comprehensive offerings of mid-range fpgas ranging from the lowest power for 6 gigabits per second (gbps) and 10 gbps applications, to the highest mid-range fpga bandwidth 12.5 gbps transceivers. the arria v devices are ideal for power-sensitive wireless infrastructure equipment, 20g/40g bridging, switching, and packet processing applications, high-definition video processing and image manipulation, and intensive digital signal processing (dsp) applications. related information arria v device handbook: known issues lists the planned updates to the arria v device handbook chapters. key advantages of arria v devices table 1: key advantages of the arria v device family supporting feature advantage ? built on tsmc's 28 nm process technology and includes an abundance of hard intellectual property (ip) blocks ? power-optimized multitrack routing and core architecture ? up to 50% lower power consumption than the previous generation device ? lowest power transceivers of any midrange family lowest static power in its class ? 8-input adaptive logic module (alm) ? up to 38.38 megabits (mb) of embedded memory ? variable-precision digital signal processing (dsp) blocks improved logic integration and differentiation capabilities ? serial data rates up to 12.5 gbps ? hard memory controllers increased bandwidth capacity ? tight integration of a dual-core arm cortex-a9 mpcore processor, hard ip, and an fpga in a single arria v system-on-a-chip (soc) fpga ? supports over 128 gbps peak bandwidth with integrated data coherency between the processor and the fpga fabric hard processor system (hps) with integrated arm ? cortex ? -a9 mpcore processor iso 9001:2008 registered ? 2013 altera corporation. all rights reserved. al tera, arria, cyclone, hardcopy , max, megacore, nios, quar tus and stra tix words and logos are trademarks of altera corporation and registered in the u.s. patent and t rademark of fice and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www .altera.com/common/legal.html. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty , but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. subscribe feedback www.altera.com 101 inno v ation dr iv e , san jose , ca 95134
supporting feature advantage ? requires as low as four power supplies to operate ? available in thermal composite flip chip ball-grid array (bga) packaging ? includes innovative features such as configuration via protocol (cvp), partial reconfiguration, and design security lowest system cost summary of arria v features table 2: summary of features for arria v devices description feature ? tsmc's 28-nm process technology: ? arria v gx , gt, sx, and st28-nm low power (28lp) process ? arria v gz 28-nm high performance (28hp) process ? lowest static power in its class (less than 1.2 w for 500k logic elements (les) at 85c junction under typical conditions) ? 0.85 v , 1.1 v , or 1.15 v core nominal voltage technology ? thermal composite flip chip bga packaging ? multiple device densities with identical package footprints for seamless migration between different device densities ? lead, lead-free (pb-free), and rohs-compliant options packaging ? enhanced 8-input alm with four registers ? improved routing architecture to reduce congestion and improve compilation time high-performance fpga fabric ? m10k10-kilobits (kb) memory blocks with soft error correction code (ecc) ( arria v gx , gt, sx, and st devices only) ? m20k20-kb memory blocks with hard ecc ( arria v gz devices only) ? memory logic array block (mlab)-640-bit distributed lutram where you can use up to 50% of the alms as mlab memory internal memory blocks arria v device overview altera corporation av-51001 summary of arria v features 2 2013.05.06 feedback
description feature ? native support for up to four signal processing precision levels: ? three 9 x 9 , two 18 x 18 , or one 27 x 27 multiplier in the same variable-precision dsp block ? one 36 x 36 multiplier using two variable-precision dsp blocks ( arria v gz devices only) ? 64-bit accumulator and cascade for systolic finite impulse responses (firs) ? embedded internal coefficient memory ? preadder/subtractor for improved efficiency variable-precision dsp embedded hard ip blocks ddr3 and ddr2 memory controller ( arria v gx , gt, sx, and st only) ? custom implementation: ? arria v gx and sx devicesup to 6.5536 gbps ? arria v gt and st devicesup to 10.3125 gbps ? arria v gz devicesup to 12.5 gbps ? pci express ? ( pcie ? ) gen2 (x1, x2, or x4) and gen1 (x1, x2, x4, or x8) hard ip with multifunction support, endpoint, and root port ? pcie gen3 (x1, x2, x4, or x8) support ( arria v gz only) ? gbps ethernet (gbe) and xaui physical coding sublayer (pcs) ? common public radio interface (cpri) pcs ? gigabit-capable passive optical network (gpon) pcs ? 10-gbps ethernet (10gbe) pcs ? serial rapidio ? (srio) pcs ? interlaken pcs embedded transceiver i/o ? up to 650 mhz global clock network ? global, quadrant, and peripheral clock networks ? clock networks that are not used can be powered down to reduce dynamic power clock networks ? high-resolution fractional plls ? precision clock synthesis, clock delay compensation, and zero delay buffering (zdb) ? integer mode and fractional mode ? lc oscillator atx transmitter plls ( arria v gz only) phase-locked loops (plls) altera corporation arria v device overview 3 summary of arria v features av-51001 2013.05.06 feedback
description feature ? 1.6 gbps lvds receiver and transmitter ? 800 mhz / 1.6 gbps external memory interface ? on-chip termination (oct) ? 3.3 v support 1 fpga general-purpose i/os (gpios) memory interfaces with low latency: ? hard memory controller-up to 1.066 gbps ? soft memory controller-up to 1.6 gbps external memory interface ? 600 mbps to 12.5 gbps integrated transceiver speed ? less than 105 mw per channel at 6 gbps , less than 165 mw per channel at 10 gbps , and less than 170 mw per channel at 12.5 gbps ? transmit pre-emphasis and receiver equalization ? dynamic partial reconfiguration of individual channels ? physical medium attachment (pma) with soft pcs that supports 9.8304 gbps cpri ( arria v gt and st only) ? pma with hard pcs that supports up to 9.8 gbps cpri ( arria v gz only) ? hard pcs that supports 10gbase-r and 10gbase-kr ( arria v gz only) low-power high-speed serial interface ? dual-core arm cortex-a9 mpcore processor-up to 800 mhz maximum frequency with support for symmetric and asymmetric multiprocessing ? interface peripherals10/100/1000 ethernet media access control (emac), usb 2.0 on-the-go (otg) controller, quad serial peripheral interface (qspi) flash controller, nand flash controller, secure digital/multimediacard (sd/mmc) controller, uart, serial peripheral interface (spi), i2c interface, and up to 85 hps gpio interfaces ? system peripheralsgeneral-purpose timers, watchdog timers, direct memory access (dma) controller, fpga configuration manager, and clock and reset managers ? on-chip ram and boot rom ? hpsCfpga bridgesinclude the fpga-to-hps, hps-to-fpga, and lightweight hps-to-fpga bridges that allow the fpga fabric to issue transactions to slaves in the hps, and vice versa ? fpga-to-hps sdram controller subsystemprovides a configurable interface to the multiport front end (mpfe) of the hps sdram controller ? arm coresight ? jtag debug access port, trace port, and on-chip trace storage hps ( arria v sx and st devices only) ? tamper protection-comprehensive design protection to protect your valuable ip investments ? enhanced advanced encryption standard (aes) design security features ? cvp ? partial and dynamic reconfiguration of the fpga ? active serial (as) x1 and x4, passive serial (ps), jtag, and fast passive parallel (fpp) x8, x16, and x32 ( arria v gz ) configuration options ? remote system upgrade configuration 1 arria v gz devices support 3.3 v with a 3.0 v v ccio . arria v device overview altera corporation av-51001 summary of arria v features 4 2013.05.06 feedback
arria v device variants and packages table 3: device variants for the arria v device family description variant fpga with integrated 6.5536 gbps transceivers that provides bandwidth, cost, and power levels that are optimized for high-volume data and signal-processing applications arria v gx fpga with integrated 10.3125 gbps transceivers that provides enhanced high-speed serial i/o bandwidth for cost-sensitive data and signal processing applications arria v gt fpga with integrated 12.5 gbps transceivers that provides enhanced high-speed serial i/o bandwidth for high-performance and cost-sensitive data and signal processing applications arria v gz soc fpga with integrated arm-based hps and 6.5536 gbps transceivers arria v sx soc fpga with integrated arm-based hps and 10.3125 gbps transceivers arria v st arria v gx this section provides the available options, maximum resource counts, and package plan for the arria v gx devices. available options figure 1: sample ordering code and available options for arria v gx devicespreliminary altera corporation arria v device overview 5 arria v device variants and packages av-51001 2013.05.06 family signature embedded hard ips t ransceiver count t ransceiver speed grade package t ype package code operating t emperature fpga fabric speed grade optional suf fix indicates specific device options or shipment method gx : 6-gbps transceivers b : no hard pcie or hard memory controller m : 1 hard pcie and 2 hard memory controllers f : maximum 2 hard pcie and 4 hard memory controllers 5a : arria v a1: 75k logic elements a3: 156k logic elements a5: 190k logic elements a7: 242k logic elements b1: 300k logic elements b3: 362k logic elements b5: 420k logic elements b7: 504k logic elements d : 9 g : 18 h : 24 k : 36 4 : 6.5536 gbps 6 : 3.1250 gbps f : fineline bga (fbga) 27 : 672 pins 31 : 896 pins 35 : 1,152 pins 40 : 1,517 pins c : commercial (t j = 0 c to 85 c) i : industrial (t j = -40 c to 100 c) 3 (fastest) 4 5 6 n : lead-free packaging es : engineering sample 5a gx f b5 h 4 f 35 i 3 n member code family v ariant feedback
maximum resources table 4: maximum resource counts for arria v gx devicespreliminary member code resource b7 b5 b3 b1 a7 a5 a3 a1 504 420 362 300 242 190 156 75 logic elements (le) (k) 190,240 158,491 136,880 113,208 91,680 71,698 58,900 28,302 alm 760,960 633,964 547,520 452,832 366,720 286,792 235,600 113,208 register 24,140 20,540 17,260 15,100 13,660 11,800 10,510 8,000 m10k memory (kb) 2,906 2,532 2,098 1,852 1,448 1,173 961 463 mlab 1,156 1,092 1,045 920 800 600 396 240 variable-precision dsp block 2,312 2,184 2,090 1,840 1,600 1,200 792 480 18 x 18 multiplier 16 16 12 12 12 12 10 10 pll 2 36 36 24 24 24 24 9 9 6 gbps transceiver 704 704 704 704 544 544 416 416 gpio 3 160 160 160 160 120 120 68 68 transmitter lvds 176 176 176 176 136 136 80 80 receiver 2 2 2 2 2 2 1 1 pcie hard ip block 4 4 4 4 4 4 2 2 hard memory controller related information high-speed differential i/o interfaces and dpa in arria v devices chapter, arria v device handbook provides the number of lvds channels in each device package. 2 the number of plls includes general-purpose fractional plls and transceiver fractional plls. 3 the number of gpios does not include transceiver i/os . in the quartus ii software, the number of user i/os includes transceiver i/os . arria v device overview altera corporation av-51001 maximum resources 6 2013.05.06 feedback
package plan table 5: package plan for arria v gx devicespreliminary f1517 (40 mm) f1152 (35 mm) f896 4 (31 mm) f672 (27 mm) member code xcvr gpio xcvr gpio xcvr gpio xcvr gpio 9 416 9 336 a1 9 416 9 336 a3 24 544 18 384 9 336 a5 24 544 18 384 9 336 a7 24 704 24 544 18 384 b1 24 704 24 544 18 384 b3 36 704 24 544 b5 36 704 24 544 b7 arria v gt this section provides the available options, maximum resource counts, and package plan for the arria v gt devices. available options figure 2: sample ordering code and available options for arria v gt devicespreliminary 4 in the f896 package, the pcie hard ip block on the right side of the arria v gx a5, a7, b1, and b3 devices support x1 for gen1 and gen2 data rates. altera corporation arria v device overview 7 package plan av-51001 2013.05.06 family signature embedded hard ips t ransceiver count maximum channels t ransceiver speed grade package t ype package code operating t emperature fpga fabric speed grade optional suf fix indicates specific device options or shipment method gt : 10-gbps transceivers m : 1 hard pcie and 2 hard memory controllers f : maximum 2 hard pcie and 4 hard memory controllers 5a : arria v c3 : 156k logic elements c7 : 242k logic elements d3 : 362k logic elements d7 : 504k logic elements d : 9 g : 18 h : 24 k : 36 3 : 10.3125 gbps f : fineline bga (fbga) 27 : 672 pins 31 : 896 pins 35 : 1,152 pins 40 : 1,517 pins 3 (fastest) 5 n : lead-free packaging es : engineering sample 5a gt f d7 k 3 f 40 i 3 n member code family v ariant i : industrial (t j = -40 c to 100 c) feedback
maximum resources table 6: maximum resource counts for arria v gt devicespreliminary member code resource d7 d3 c7 c3 504 362 242 156 logic elements (le) (k) 190,240 136,880 91,680 58,900 alm 760,960 547,520 366,720 235,600 register 24,140 17,260 13,660 10,510 m10k memory (kb) 2,906 2,098 1,448 961 mlab 1,156 1,045 800 396 variable-precision dsp block 2,312 2,090 1,600 792 18 x 18 multiplier 16 12 12 10 pll 5 6 (36) 6 (24) 6 (24) 3 (9) 6 gbps 6 transceiver 20 12 12 4 10 gbps 7 704 704 544 416 gpio 8 160 160 120 68 transmitter lvds 176 176 136 80 receiver 2 2 2 1 pcie hard ip block 4 4 4 2 hard memory controller related information high-speed differential i/o interfaces and dpa in arria v devices chapter, arria v device handbook provides the number of lvds channels in each device package. transceiver architecture in arria v devices describes 10 gbps channels usage conditions. 5 the number of plls includes general-purpose fractional plls and transceiver fractional plls. 6 the 6 gbps transceiver counts are for dedicated 6-gbps channels. you can also configure any pair of 10 gbps channels as three 6 gbps channels-the total number of 6 gbps channels are shown in brackets. 7 chip-to-chip connections only. for 10 gbps channel usage conditions, refer to the transceiver architecture in arria v devices chapter. for information about 10 gbps sff-8431 compliance, contact altera. 8 the number of gpios does not include transceiver i/os . in the quartus ii software, the number of user i/os includes transceiver i/os . arria v device overview altera corporation av-51001 maximum resources 8 2013.05.06 feedback
package plan table 7: package plan for arria v gt devicespreliminary f1517 ( 40 mm ) f1152 ( 35 mm ) f896 ( 31 mm ) f672 ( 27 mm ) mem- ber code xcvr gpio xcvr gpio xcvr gpio xcvr gpio 10- gbps 6-gbps 10- gbps 6-gbps 10- gbps 6-gbps 10- gbps 6-gbps 4 3 (9) 416 4 3 (9) 336 c3 12 6 (24) 544 8 6 (18) 384 c7 12 6 (24) 704 12 6 (24) 544 8 6 (18) 384 d3 20 6 (36) 704 12 6 (24) 544 d7 the 6-gbps transceiver counts are for dedicated 6-gbps channels. you can also configure any pair of 10-gbps channels as three 6-gbps channelsthe total number of 6-gbps channels are shown in brackets. for example, you can also configure the arria v gt d7 device in the f1517 package with nine 6-gbps and eighteen 10-gbps, twelve 6-gbps and sixteen 10-gbps, fifteen 6-gbps and fourteen 10-gbps, or up to thirty-six 6-gbps with no 10-gbps channels. arria v gz this section provides the available options, maximum resource counts, and package plan for the arria v gz devices. available options figure 3: sample ordering code and available options for arria v gz devicespreliminary altera corporation arria v device overview 9 package plan av-51001 2013.05.06 family signature embedded hard ips t ransceiver count maximum channels t ransceiver speed grade package t ype package code operating t emperature fpga fabric speed grade optional suffix indicates specific device options or shipment method gz : 12.5-gbps transceivers m : 1 hard pcie controller 5a : arria v e1 : 220k logic elements e3 : 360k logic elements e5 : 400k logic elements e7 : 450k logic elements e : 12 h : 24 k : 36 2 : 12.5 gbps 3 : 10.3125 gbps f : fineline bga (fbga) h : hybrid fbga 29 : 780 pins 35 : 1,152 pins 40 : 1,517 pins 3 (fastest) 4 n : lead-free packaging l : low-power device 5a gz m e7 k 2 f 40 c 3 n member code family v ariant c : commercial (t j = 0 c to 85 c) i : industrial (t j = -40 c to 100 c) note: low-power device option is available only for C3 speed grade at industrial temperature feedback
maximum resources table 8: maximum resource counts for arria v gz devicespreliminary member code resource e7 e5 e3 e1 450 400 360 220 logic elements (le) (k) 169,800 150,960 135,840 83,020 alm 679,200 603,840 543,360 332,080 register 34,000 28,800 19,140 11,700 m20k memory (kb) 5,306 4,718 4,245 2,594 mlab 1,139 1,092 1,044 800 variable-precision dsp block 2,278 2,184 2,088 1,600 18 x 18 multiplier 24 24 20 20 pll 9 36 36 24 24 12.5 gbps transceiver 674 674 414 414 gpio 10 166 166 99 99 transmitter lvds 11 168 168 108 108 receiver 1 1 1 1 pcie hard ip block related information high-speed differential i/o interfaces and dpa in arria v devices chapter, arria v device handbook provides the number of lvds channels in each device package. package plan table 9: package plan for arria v gz devicespreliminary f1517 ( 40 mm ) f1152 ( 35 mm ) h780 ( 29 mm ) member code xcvr gpio xcvr gpio xcvr gpio 24 414 12 342 e1 24 414 12 342 e3 36 674 24 534 e5 36 674 24 534 e7 9 the number of plls includes general-purpose fractional plls and transceiver fractional plls. 10 the number of gpios does not include transceiver i/os . in the quartus ii software, the number of user i/os includes transceiver i/os . 11 arria v device overview altera corporation av-51001 maximum resources 10 2013.05.06 feedback
arria v sx this section provides the available options, maximum resource counts, and package plan for the arria v sx devices. available options figure 4: sample ordering code and available options for arria v sx devicespreliminary the C3 fpga fabric speed grade is available only for industrial temperature devices. maximum resources table 10: maximum resource counts for arria v sx devicespreliminary member code resource b5 b3 462 350 logic elements (le) (k) 174,340 132,075 alm 697,360 528,300 register 22,820 17,290 m10k memory (kb) 2,658 2,014 mlab 1,090 809 variable-precision dsp block 2,180 1,618 18 x 18 multiplier 14 14 fpga pll 12 12 the number of plls includes general-purpose fractional plls and transceiver fractional plls. altera corporation arria v device overview 1 1 arria v sx av-51001 2013.05.06 family signature embedded hard ips t ransceiver count t ransceiver speed grade package t ype package code operating t emperature fpga fabric speed grade optional suf fix indicates specific device options or shipment method sx : soc fpga with 6-gbps transceivers b : no hard pcie or hard memory controllers m : maximum 1 hard pcie controllers and 2 hard memory controllers f : maximum 2 hard pcie controllers and 3 hard memory controllers 5a : arria v b3 : 350k logic elements b5 : 462k logic elements d : 9 e : 12 g : 18 h : 30 4 : 6.5336 gbps f : fineline bga (fbga) 31 : 896 pins 35 : 1,152 pins 40 : 1,517 pins c : commercial (t j = 0 c to 85 c) i : industrial (t j = -40 c to 100 c) 3 (fastest) 4 5 6 n : lead-free packaging es : engineering sample 5a sx f b5 h 4 f 40 i 3 n member code family v ariant feedback
member code resource b5 b3 3 3 hps pll 30 30 6 gbps transceiver 528 528 fpga gpio 13 208 208 hps i/o 121 121 transmitter lvds 136 136 receiver 2 2 pcie hard ip block 3 3 fpga hard memory controller 1 1 hps hard memory controller dual-core dual-core arm cortex-a9 mpcore processor related information high-speed differential i/o interfaces and dpa in arria v devices chapter, arria v device handbook provides the number of lvds channels in each device package. package plan table 11: package plan for arria v sx devicespreliminary f1517 ( 40 mm ) f1152 ( 35 mm ) f896 ( 31 mm ) member code xcvr hps i/o fpga gpio xcvr hps i/o fpga gpio xcvr hps i/o fpga gpio 30 208 528 18 208 350 12 208 170 b3 30 208 528 18 208 350 12 208 170 b5 arria v st this section provides the available options, maximum resource counts, and package plan for the arria v st devices. 13 the number of gpios does not include transceiver i/os . in the quartus ii software, the number of user i/os includes transceiver i/os . arria v device overview altera corporation av-51001 package plan 12 2013.05.06 feedback
available options figure 5: sample ordering code and available options for arria v st devicespreliminary maximum resources table 12: maximum resource counts for arria v st devicespreliminary member code resource d5 d3 462 350 logic elements (le) (k) 174,340 132,075 alm 697,360 528,300 register 22,820 17,290 m10k memory (kb) 2,658 2,014 mlab 1,090 809 variable-precision dsp block 2,180 1,618 18 x 18 multiplier 14 14 fpga pll 14 3 3 hps pll 30 30 6-gbps transceiver 16 16 10-gbps 15 14 the number of plls includes general-purpose fractional plls and transceiver fractional plls. 15 chip-to-chip connections only. for 10 gbps channel usage conditions, refer to the transceiver architecture in arria v devices chapter. for information about 10 gbps sff-8431 compliance, contact altera. altera corporation arria v device overview 13 available options av-51001 2013.05.06 family signature embedded hard ips t ransceiver count maximum channels t ransceiver speed grade package t ype package code operating t emperature fpga fabric speed grade optional suffix indicates specific device options or shipment method st : soc fpga with 10-gbps transceivers m : maximum 1 hard pcie controller and 2 hard memory controllers f : maximum 2 hard pcie controllers and 3 hard memory controllers 5a : arria v d3 : 350k logic elements d5 : 462k logic elements e : 12 g : 18 k : 30 3 : 10.3125 gbps f : fineline bga (fbga) 31 : 896 pins 35 : 1,152 pins 40 : 1,517 pins i : industrial (t j = -40 c to 100 c) 3 (fastest) 5 n : lead-free packaging es : engineering sample 5a st f d5 k 3 f 40 i 3 n member code family v ariant feedback
member code resource d5 d3 540 528 fpga gpio 16 210 208 hps i/o 121 121 transmitter lvds 136 136 receiver 2 2 pcie hard ip block 3 3 fpga hard memory controller 1 1 hps hard memory controller dual-core dual-core arm cortex-a9 mpcore processor related information high-speed differential i/o interfaces and dpa in arria v devices chapter, arria v device handbook provides the number of lvds channels in each device package. transceiver architecture in arria v devices describes 10 gbps channels usage conditions. package plan table 13: package plan for arria v st devicespreliminary f1517 ( 40 mm ) f1152 ( 35 mm ) f896 ( 31 mm ) mem- ber code xcvr hps i/o fpga gpio xcvr hps i/o fpga gpio xcvr hps i/o fpga gpio 10 gbps 6 gbps 10 gbps 6 gbps 10 gbps 6 gbps 16 30 208 528 8 18 208 350 6 12 208 170 d3 16 30 208 528 8 18 208 350 6 12 208 170 d5 16 the number of gpios does not include transceiver i/os . in the quartus ii software, the number of user i/os includes transceiver i/os . arria v device overview altera corporation av-51001 package plan 14 2013.05.06 feedback
i/o vertical migration for arria v devices figure 6: vertical migration capability across arria v device packages and densitiespreliminary the arrows indicate the vertical migration paths. some packages have several migration paths. the devices included in each vertical migration path are shaded. you can also migrate your design across device densities in the same package option if the devices have the same dedicated pins, configuration pins, and power pins. you can achieve the vertical migration shaded in red if you use only up to 320 gpios, up to nine 6 gbps transceiver channels, and up to four 10 gbps transceiver (for arria v gt devices). this migration path is not shown in the quartus ii software pin migration view. to verify the pin migration compatibility, use the pin migration view window in the quartus ? ii software pin planner. note: except for arria v gx a5 and a7, and arria v gt c7 devices, all other arria v gx and gt devices require a specific power-up sequence. if you plan to migrate your design from arria v gx a5 and note: a7, and arria v gt c7 devices to other arria v devices, your design must adhere to the same required power-up sequence. related information i/o management chapter, quartus ii handbook more information about vertical i/o migrations. power management in arria v devices describes the power-up sequence required for arria v gx and gt devices. altera corporation arria v device overview 15 i/o vertical migration for arria v devices av-51001 2013.05.06 v ariant member code package f672 f780 f896 f 1 152 f1517 arria v gx a1 a3 a5 a7 b1 b3 b5 b7 arria v gt c3 c7 d3 d7 arria v gz e1 e3 e5 e7 arria v sx b3 b5 arria v st d3 d5 feedback
adaptive logic module arria v devices use a 28 nm alm as the basic building block of the logic fabric. the alm, as shown in following figure, uses an 8-input fracturable look-up table (lut) with four dedicated registers to help improve timing closure in register-rich designs and achieve an even higher design packing capability than previous generations. figure 7: alm for arria v devices you can configure up to 50% of the alms in the arria v devices as distributed memory using mlabs. related information embedded memory capacity in arria v devices on page 19 lists the embedded memory capacity for each device. variable-precision dsp block arria v devices feature a variable-precision dsp block that supports these features: ? configurable to support signal processing precisions ranging from 9 x 9, 18 x 18, 27 x 27, and 36 x 36 bits natively ? a 64-bit accumulator ? double accumulator ? a hard preadder that is available in both 18- and 27-bit modes ? cascaded output adders for efficient systolic finite impulse response (fir) filters ? dynamic coefficients ? 18-bit internal coefficient register banks ? enhanced independent multiplier operation ? efficient support for single-precision floating point arithmetic ? the inferability of all modes by the quartus ii design software arria v device overview altera corporation av-51001 adaptive logic module 16 2013.05.06 fpga device 1 2 3 4 5 6 7 8 adaptive lut full adder reg reg full adder reg reg feedback
table 14: variable-precision dsp block configurations for arria v devices dsp block resource multiplier size (bit) usage example 1 three 9 x 9 low precision fixed point for video applications 1 two 18 x 18 medium precision fixed point in fir filters 1 two 18 x 18 with accumulate fir filters 1 one 27 x 27 single-precision floating-point implementations 2 one 36 x 36 very high precision fixed point implementations you can configure each dsp block during compilation as independent three 9 x 9 , two 18 x 18 , or one 27 x 27 multipliers. using two dsp block resources, you can also configure a 36 x 36 multiplier for high-precision applications. with a dedicated 64 bit cascade bus, you can cascade multiple variable-precision dsp blocks to implement even higher precision dsp functions efficiently. table 15: number of multipliers in arria v devices the table lists the variable-precision dsp resources by bit precision for each arria v device. 18 x 18 mul- tiplier adder summed with 36 bit input 18 x 18 mul- tiplier adder mode independent input and output multiplications operator variable- precision dsp block mem- ber code variant 36 x 36 mul- tiplier 27 x 27 mul- tiplier 18 x 18 mul- tiplier 9 x 9 multi- plier 240 240 240 480 720 240 a1 arria v gx 396 396 396 792 1,188 396 a3 600 600 600 1,200 1,800 600 a5 800 800 800 1,600 2,400 800 a7 920 920 920 1,840 2,760 920 b1 1,045 1,045 1,045 2,090 3,135 1,045 b3 1,092 1,092 1,092 2,184 3,276 1,092 b5 1,156 1,156 1,156 2,312 3,468 1,156 b7 396 396 396 792 1,188 396 c3 arria v gt 800 800 800 1,600 2,400 800 c7 1,045 1,045 1,045 2,090 3,135 1,045 d3 1,156 1,156 1,156 2,312 3,468 1,156 d7 altera corporation arria v device overview 17 variable-precision dsp block av-51001 2013.05.06 feedback
18 x 18 mul- tiplier adder summed with 36 bit input 18 x 18 mul- tiplier adder mode independent input and output multiplications operator variable- precision dsp block mem- ber code variant 36 x 36 mul- tiplier 27 x 27 mul- tiplier 18 x 18 mul- tiplier 9 x 9 multi- plier 800 800 400 800 1,600 2,400 800 e1 arria v gz 1,044 1,044 522 1,044 2,088 3,132 1,044 e3 1,092 1,092 546 1,092 2,184 3,276 1,092 e5 1,139 1,139 569 1,139 2,278 3,417 1,139 e7 809 809 809 1,618 2,427 809 b3 arria v sx 1,090 1,090 1,090 2,180 3,270 1,090 b5 809 809 809 1,618 2,427 809 d3 arria v st 1,090 1,090 1,090 2,180 3,270 1,090 d5 embedded memory blocks the embedded memory blocks in the devices are flexible and designed to provide an optimal amount of small- and large-sized memory arrays to fit your design requirements. types of embedded memory the arria v devices contain two types of memory blocks: ? 20 kb m20k or 10 kb m10k blocksblocks of dedicated memory resources. the m20k and m10k blocks are ideal for larger memory arrays while still providing a large number of independent ports. ? 640 bit memory logic array blocks (mlabs)enhanced memory blocks that are configured from dual-purpose logic array blocks (labs). the mlabs are ideal for wide and shallow memory arrays. the mlabs are optimized for implementation of shift registers for digital signal processing (dsp) applications, wide shallow fifo buffers, and filter delay lines. each mlab is made up of ten adaptive logic modules (alms). in the arria v devices, you can configure these alms as ten 32 x 2 blocks, giving you one 32 x 20 simple dual-port sram block per mlab. you can also configure these alms , in arria v gz devices, as ten 64 x 1 blocks, giving you one 64 x 10 simple dual-port sram block per mlab. arria v device overview altera corporation av-51001 embedded memory blocks 18 2013.05.06 feedback
embedded memory capacity in arria v devices table 16: embedded memory capacity and distribution in arria v devices total ram bit (kb) mlab m10k m20k member code variant ram bit (kb) block ram bit (kb) block ram bit (kb) block 8,463 463 741 8,000 800 a1 arria v gx 11,471 961 1538 10,510 1,051 a3 12,973 1,173 1877 11,800 1,180 a5 15,108 1,448 2317 13,660 1,366 a7 16,952 1,852 2964 15,100 1,510 b1 19,358 2,098 3357 17,260 1,726 b3 23,072 2,532 4052 20,540 2,054 b5 27,046 2,906 4650 24,140 2,414 b7 11,471 961 1538 10,510 1,051 c3 arria v gt 15,108 1,448 2317 13,660 1,366 c7 19,358 2,098 3357 17,260 1,726 d3 27,046 2,906 4650 24,140 2,414 d7 14,294 2,594 4,151 11,700 585 e1 arria v gz 23,385 4,245 6,792 19,140 957 e3 33,518 4,718 7,548 28,800 1,440 e5 39,306 5,306 8,490 34,000 1,700 e7 19,304 2,014 3223 17,290 1,729 b3 arria v sx 25,478 2,658 4253 22,820 2,282 b5 19,304 2,014 3223 17,290 1,729 d3 arria v st 25,478 2,658 4253 22,820 2,282 d5 altera corporation arria v device overview 19 embedded memory capacity in arria v devices av-51001 2013.05.06 feedback
embedded memory configurations table 17: supported embedded memory block configurations for arria v devices this table lists the maximum configurations supported for the embedded memory blocks. the information is applicable only to the single-port ram and rom modes. programmable width depth (bits) memory block x16, x18, or x20 32 mlab x10 64 17 x40 512 m20k x20 1k x10 2k x5 4k x2 8k x1 16k x40 or x32 256 m10k x20 or x16 512 x10 or x8 1k x5 or x4 2k x2 4k x1 8k clock networks and pll clock sources arria v devices have 16 global clock networks capable of up to 650 mhz operation. the clock network architecture is based on altera's global, quadrant, and peripheral clock structure. this clock structure is supported by dedicated clock input pins and fractional plls. to reduce power consumption, the quartus ii software identifies all unused sections of the clock network and powers them down. note: pll features the plls in the arria v devices support the following features: ? frequency synthesis ? on-chip clock deskew ? jitter attenuation ? counter reconfiguration ? programmable output clock duty cycles ? pll cascading 17 available for arria v gz devices only. arria v device overview altera corporation av-51001 embedded memory configurations 20 2013.05.06 feedback
? reference clock switchover ? programmable bandwidth ? dynamic phase shift ? zero delay buffers fractional pll in addition to integer plls, the arria v devices use a fractional pll architecture. the devices have up to 16 plls, each with 18 output counters. one fractional pll can use up to 18 output counters and two adjacent fractional plls share the 18 output counters. you can use the output counters to reduce pll usage in two ways: ? reduce the number of oscillators that are required on your board by using fractional plls ? reduce the number of clock pins that are used in the device by synthesizing multiple clock frequencies from a single reference clock source if you use the fractional pll mode, you can use the plls for precision fractional-n frequency synthesisremoving the need for off-chip reference clock sources in your design. the transceiver fractional plls that are not used by the transceiver i/os can be used as general purpose fractional plls by the fpga fabric. fpga general purpose i/o arria v devices offer highly configurable gpios. the following list describes the features of the gpios: ? programmable bus hold and weak pull-up ? lvds output buffer with programmable differential output voltage (v od ) and programmable pre-emphasis ? on-chip parallel termination ( r t oct ) for all i/o banks with oct calibration to limit the termination impedance variation ? on-chip dynamic termination that has the ability to swap between series and parallel termination, depending on whether there is read or write on a common bus for signal integrity ? unused voltage reference ( vref ) pins that can be configured as user i/os ( arria v gx , gt, sx, and st only) ? easy timing closure support using the hard read fifo in the input register path, and delay-locked loop (dll) delay chain with fine and coarse architecture pcie gen1 , gen2, and gen 3 hard ip arria v devices contain pcie hard ip that is designed for performance, ease-of-use , and increased functionality. the pcie hard ip consists of the mac, data link, and transaction layers. the pcie hard ip supports pcie gen3, gen 2, and gen 1 end point and root port for up to x8 lane configuration. the pcie endpoint support includes multifunction support for up to eight functions, as shown in the following figure. the integrated multifunction support reduces the fpga logic requirements by up to 20,000 les for pcie designs that require multiple peripherals. altera corporation arria v device overview 21 fpga general purpose i/o av-51001 2013.05.06 feedback
figure 8: pcie multifunction for arria v devices the arria v pcie hard ip operates independently from the core logic. this independent operation allows the pcie link to wake up and complete link training in less than 100 ms while the arria v device completes loading the programming file for the rest of the device. in addition, the pcie hard ip in the arria v device provides improved end-to-end datapath protection using ecc. external memory interface this section provides an overview of the external memory interface in arria v devices. hard and soft memory controllers arria v gx,gt, sx, and st devices support up to four hard memory controllers for ddr3 and ddr2 sdram devices. each controller supports 8 to 32 bit components of up to 4 gigabits (gb) in density with two chip selects and optional ecc. for the arria v soc fpga devices, an additional hard memory controller in the hps supports ddr3, ddr2, and lpddr2 sdram devices. all arria v devices support soft memory controllers for ddr3, ddr2, and lpddr2 sdram devices , qdr ii+, qdr ii, and ddr ii+ sram devices, and rldram ii devices for maximum flexibility. ddr3 sdram leveling is supported only in arria v gz devices. note: external memory performance table 18: external memory interface performance in arria v devices soft controller (mhz) hard controller (mhz) voltage (v) interface arria v gz arria v gx , gt, sx, and st arria v gx , gt, sx, and st 800 667 533 1.5 ddr3 sdram 800 667 533 1.35 400 400 400 1.8 ddr2 sdram 400 1.2 lpddr2 sdram 667 1.2 rldram 3 arria v device overview altera corporation av-51001 external memory interface 22 2013.05.06 pcie link external system fpga device host cpu memory controller root complex local peripheral 1 local peripheral 2 pcie rp pcie ep can gbe a t a bridge to pcie spi gpio i 2 c usb feedback
soft controller (mhz) hard controller (mhz) voltage (v) interface arria v gz arria v gx , gt, sx, and st arria v gx , gt, sx, and st 533 400 1.8 rldram ii 533 400 1.5 500 400 1.8 qdr ii+ sram 500 400 1.5 333 400 1.8 qdr ii sram 333 400 1.5 400 1.8 ddr ii+ sram 18 400 1.5 hps external memory performance table 19: hps external memory interface performance the hard processor system (hps) is available in arria v soc fpga devices only. hps hard controller (mhz) voltage (v) interface 533 1.5 ddr3 sdram 533 1.35 400 1.8 ddr2 sdram 400 1.5 333 1.2 lpddr2 sdram low-power serial transceivers arria v devices deliver the industry's lowest power consumption per transceiver channel: ? 12.5 gbps transceivers at less than 170 mw ? 10 gbps transceivers at less than 165 mw ? 6 gbps transceivers at less than 105 mw arria v transceivers are designed to be compliant with a wide range of protocols and data rates. transceiver channels the transceivers are positioned on the left and right outer edges of the device. the transceiver channels consist of the physical medium attachment (pma), physical coding sublayer (pcs), and clock networks. 18 not available as altera ? ip. altera corporation arria v device overview 23 hps external memory performance av-51001 2013.05.06 feedback
the following figures are graphical representations of a top view of the silicon die, which corresponds to a reverse view for flip chip packages. different arria v devices may have different floorplans than the ones shown in the figures. figure 9: device chip overview for arria v gx and gt devices arria v device overview altera corporation av-51001 transceiver channels 24 2013.05.06 i/o, l vds, and memory interface i/o, l vds, and memory interface t ransceiver pma blocks t ransceiver pma blocks hard pcs blocks hard pcs blocks pcie hard ip blocks pcie hard ip blocks fractional plls fractional plls hard memory controller hard memory controller core logic fabric and mlabs v ariable-precision dsp blocks m10k internal memory blocks t ransceiver pma t ransceiver pma t ransceiver pma hard pcs hard pcs hard pcs clock networks t ransceiver individual channels feedback
figure 10: device chip overview for arria v gz devices figure 11: device chip overview for arria v sx and st devices altera corporation arria v device overview 25 transceiver channels av-51001 2013.05.06 i/o, l vds, and memory interface i/o, l vds, and memory interface t ransceiver pma blocks t ransceiver pma blocks hard pcs blocks hard pcs blocks pcie hard ip blocks pcie hard ip blocks fractional plls fractional plls core logic fabric and mlabs v ariable-precision dsp blocks m20k internal memory blocks t ransceiver pma t ransceiver pma t ransceiver pma hard pcs hard pcs hard pcs clock networks t ransceiver individual channels fpga i/o, l vds, and memory interface fpga i/o, l vds, and memory interface t ransceiver pma blocks t ransceiver pma blocks hard pcs blocks hard pcs blocks pcie hard ip blocks pcie hard ip blocks fractional plls fractional plls fpga hard memory controller fpga hard memory controller core logic fabric and mlabs v ariable-precision dsp blocks m10k internal memory blocks t ransceiver pma t ransceiver pma t ransceiver pma hard pcs hard pcs hard pcs clock networks t ransceiver individual channels hps memory controller hps hps i/o hps memory interface feedback
pma features to prevent core and i/o noise from coupling into the transceivers, the pma block is isolated from the rest of the chipensuring optimal signal integrity. for the transceivers, you can use the channel pll of an unused receiver pma as an additional transmit pll. table 20: pma features of the transceivers in arria v devices capability features ? arria v gx , gt, sx, and st devicesdriving capability at 6.5536 gbps with up to 25 db channel loss ? arria v gz devicesdriving capability at 12.5 gbps with up to 16 db channel loss backplane support ? arria v gx , gt, sx, and st devicesup to 10.3125 gbps ? arria v gz devicesup to 12.5 gbps chip-to-chip support superior jitter tolerance pll-based clock recovery flexible serdes width programmable serializer and deserializer (serdes) ? arria v gx , gt, sx, and st devicesup to 14.37 db of pre-emphasis and up to 4.7 db of equalization ? arria v gz devices 4-tap pre-emphasis and de-emphasis equalization and pre-emphasis 611 mbps to 10.3125 gbps ring oscillator transmit plls 600 mbps to 12.5 gbps lc oscillator atx transmit plls ( arria v gz devices only) 27 mhz to 710 mhz input reference clock range allows the reconfiguration of a single channel without affecting the operation of other channels transceiver dynamic reconfiguration pcs features the arria v core logic connects to the pcs through an 8, 10, 16, 20, 32, 40, 64, 66, or 67 bit interface, depending on the transceiver data rate and protocol. arria v devices contain pcs hard ip to support pcie gen1 , gen2, and gen3, gbe, serial rapidio ? (srio), gpon, and cpri. all other standard and proprietary protocols within the following speed ranges are also supported: ? 611 mbps to 6.5536 gbps supported through the custom double-width mode (up to 6.5536 gbps ) and custom single-width mode (up to 3.75 gbps ) of the transceiver pcs hard ip. ? 6.5536 gbps to 10.3125 gbps supported through dedicated 80 or 64 bit interface that bypass the pcs hard ip and connects the pma directly to the core logic. in arria v gz , this is supported in the transceiver pcs hard ip. arria v device overview altera corporation av-51001 pma features 26 2013.05.06 feedback
table 21: transceiver pcs features for arria v gx , gt, st, and sx devices receiver data path feature transmitter data path feature data rates (gbps) pcs support 19 ? word aligner ? 8b/10b decoder ? byte deserializer ? phase compensation fifo ? phase compensation fifo ? byte serializer ? 8b/10b encoder 0.611 to ~6.5536 custom single- and double-width modes 1.25 to 6.25 srio 1.5, 3.0, 6.0 serial ata ? word aligner ? 8b/10b decoder ? byte deserializer ? phase compensation fifo ? rate match fifo ? pipe 2.0 interface to the core logic ? phase compensation fifo ? byte serializer ? 8b/10b encoder ? pipe 2.0 interface to the core logic 2.5 and 5.0 pcie gen1 (x1, x2, x4, x8) pcie gen2 20 (x1, x2, x4) ? word aligner ? 8b/10b decoder ? byte deserializer ? phase compensation fifo ? rate match fifo ? phase compensation fifo ? byte serializer ? 8b/10b encoder 1.25 gbe ? word aligner ? 8b/10b decoder ? byte deserializer ? phase compensation fifo ? xaui state machine for realigning four channels ? deskew fifo circuitry ? phase compensation fifo ? byte serializer ? 8b/10b encoder ? xaui state machine for bonding four channels 3.125 xaui 21 ? byte deserializer ? phase compensation fifo ? phase compensation fifo ? byte serializer 0.27 22 , 1.485, 2.97 sdi 1.25 and 2.5 gpon 23 19 data rates above 6.5536 gbps up to 10.3125 gbps , such as 10gbase-r , are supported through the soft pcs. 20 pcie gen2 is supported only through the pcie hard ip. 21 xaui is supported through the soft pcs. 22 the 0.27 gbps data rate is supported using oversampling user logic that you must implement in the fpga fabric. 23 the gpon standard does not support burst mode. altera corporation arria v device overview 27 pcs features av-51001 2013.05.06 feedback
receiver data path feature transmitter data path feature data rates (gbps) pcs support 19 ? word aligner ? 8b/10b decoder ? byte deserializer ? phase compensation fifo ? rx deterministic latency ? phase compensation fifo ? byte serializer ? 8b/10b encoder ? tx deterministic latency 0.6144 to 6.144 cpri 24 table 22: transceiver pcs features for arria v gz devices receiver data path features transmitter data path features data rates (gbps) protocol ? word aligner ? deskew fifo ? rate match fifo ? 8b/10b decoder ? byte deserializer ? byte ordering ? phase compensation fifo ? byte serializer ? 8b/10b encoder ? bit-slip ? channel bonding 0.6 to 9.80 custom phy 1.25 and 2.5 gpon ? rx fifo ? gear box ? tx fifo ? gear box ? bit-slip 9.98 to 12.5 custom 10g phy ? word aligner ? deskew fifo ? rate match fifo ? 8b/10b decoder ? byte deserializer, ? byte ordering ? pipe 2.0 interface to core logic ? phase compensation fifo ? byte serializer ? 8b/10b encoder ? bit-slip ? channel bonding ? pipe 2.0 interface to core logic 2.5 and 5.0 pcie gen1 (x1, x4, x8) pcie gen2 (x1, x4, x8) ? block synchronization ? rate match fifo ? 128b/130b decoder ? descrambler ? phase compensation fifo ? phase compensation fifo ? 128b/130b encoder ? scrambler ? gear box ? bit-slip 8.0 pcie gen3 (x1, x4, x8) 19 data rates above 6.5536 gbps up to 10.3125 gbps , such as 10gbase-r , are supported through the soft pcs. 24 cpri data rates above 6.5536 gbps, such as 9.8304 gbps, are supported through the soft pcs. arria v device overview altera corporation av-51001 pcs features 28 2013.05.06 feedback
receiver data path features transmitter data path features data rates (gbps) protocol ? rx fifo ? 64b/66b decoder ? descrambler ? block synchronization ? gear box ? tx fifo ? 64b/66b encoder ? scrambler ? gear box 10.3125 10gbe ? rx fifo ? frame generator ? crc-32 checker ? frame decoder ? descrambler ? disparity checker ? block synchronization ? gear box ? tx fifo ? frame generator ? crc-32 generator ? scrambler ? disparity generator ? gear box 3.125 to 12.5 interlaken ? rx fifo ? 64b/66b decoder ? descrambler ? lane reorder ? deskew ? alignment marker lock ? block synchronization ? gear box ? destripper ? tx fifo ? 64b/66b encoder ? scrambler ? alignment marker insertion ? gearbox ? block stripper 4 x 10.3125 40gbase-r ethernet 10 x 10.3125 100gbase-r ethernet ? rx fifo ? lane deskew ? byte deserializer ? tx fifo ? channel bonding ? byte serializer (4 +1) x 11.3 40g and 100g otn (10 +1) x 11.3 ? word aligner ? deskew fifo ? rate match fifo ? 8b/10b decoder ? byte deserializer ? byte ordering ? gbe state machine ? phase compensation fifo ? byte serializer ? 8b/10b encoder ? bit-slip ? channel bonding ? gbe state machine 1.25 gbe altera corporation arria v device overview 29 pcs features av-51001 2013.05.06 feedback
receiver data path features transmitter data path features data rates (gbps) protocol ? word aligner ? deskew fifo ? rate match fifo ? 8b/10b decoder ? byte deserializer ? byte ordering ? xaui state machine for realigning four channels ? phase compensation fifo ? byte serializer ? 8b/10b encoder ? bit-slip ? channel bonding ? xaui state machine for bonding four channels 3.125 to 4.25 xaui ? word aligner ? deskew fifo ? rate match fifo ? 8b/10b decoder ? byte deserializer ? byte ordering ? srio v2.1-compliant x2 and x4 deskew state machine ? phase compensation fifo ? byte serializer ? 8b/10b encoder ? bit-slip ? channel bonding ? srio v2.1-compliant x2 and x4 channel bonding 1.25 to 6.25 srio soc fpga with hps each soc fpga combines an fpga fabric and an hps in a single device. this combination delivers the flexibility of programmable logic with the power and cost savings of hard ip in these ways: ? reduces board space, system power, and bill of materials cost by eliminating a discrete embedded processor ? allows you to differentiate the end product in both hardware and software, and to support virtually any interface standard ? extends the product life and revenue through in-field hardware and software updates hps features the hps consists of a dual-core arm cortex-a9 mpcore processor, a rich set of peripherals, and a shared multiport sdram memory controller, as shown in the following figure. arria v device overview altera corporation av-51001 soc fpga with hps 30 2013.05.06 feedback
figure 12: hps with dual-core arm cortex-a9 mpcore processor system peripherals and debug access port each ethernet mac, usb otg, nand flash controller, and sd/mmc controller module has an integrated dma controller. for modules without an integrated dma controller, an additional dma controller module provides up to eight channels of high-bandwidth data transfers. peripherals that communicate off-chip are multiplexed with other peripherals at the hps pin level. this allows you to choose which peripherals to interface with other devices on your pcb. the debug access port provides interfaces to industry standard jtag debug probes and supports arm coresight debug and core traces to facilitate software development. altera corporation arria v device overview 31 system peripherals and debug access port av-51001 2013.05.06 fpga fabric hps hps-to-fpga lightweight hps-to-fpga fpga-to-hps fpga-to-hps sdram configuration controller fpga manager 64 kb on-chip ram 64 kb boot rom level 3 interconnect ethernet mac (2x) usb otg (2x) nand flash controller sd/mmc controller dma controller stm etr (t race) debug access port arm cortex-a9 mpcore mpu subsystem cpu0 arm cortex-a9 with neon/fpu, 32 kb instruction cache, 32 kb data cache, and memory management unit cpu1 arm cortex-a9 with neon/fpu, 32 kb instruction cache, 32 kb data cache, and memory management unit scu acp level 2 cache (512 kb) multiport ddr sdram controller with optional ecc peripherals (uar t , t imer , i 2 c, w atchdog t imer , gpio, spi, clock manager , reset manager , scan manager , system manager , and quad spi flash controller) feedback
hpsCfpga axi bridges the hpsCfpga bridges, which support the advanced microcontroller bus architecture ( amba ? ) advanced extensible interface ( axi ? ) specifications, consist of the following bridges: ? fpga-to-hps axi bridgea high-performance bus supporting 32, 64, and 128 bit data widths that allows the fpga fabric to issue transactions to slaves in the hps. ? hps-to-fpga axi bridgea high-performance bus supporting 32, 64, and 128 bit data widths that allows the hps to issue transactions to slaves in the fpga fabric. ? lightweight hps-to-fpga axi bridgea lower latency 32 bit width bus that allows the hps to issue transactions to slaves in the fpga fabric. this bridge is primarily used for control and status register (csr) accesses to peripherals in the fpga fabric. the hpsCfpga axi bridges allow masters in the fpga fabric to communicate with slaves in the hps logic, and vice versa. for example, the hps-to-fpga axi bridge allows you to share memories instantiated in the fpga fabric with one or both microprocessors in the hps, while the fpga-to-hps axi bridge allows logic in the fpga fabric to access the memory and peripherals in the hps. each hpsCfpga bridge also provides asynchronous clock crossing for data transferred between the fpga fabric and the hps. hps sdram controller subsystem the hps sdram controller subsystem contains a multiport sdram controller and ddr phy that are shared between the fpga fabric (through the fpga-to-hps sdram interface), the level 2 (l2) cache, and the level 3 (l3) system interconnect. the fpga-to-hps sdram interface supports amba axi and avalon ? memory-mapped (avalon-mm) interface standards, and provides up to six individual ports for access by masters implemented in the fpga fabric. to maximize memory performance, the sdram controller subsystem supports command and data reordering, deficit round-robin arbitration with aging, and high-priority bypass features. the sdram controller subsystem supports ddr2, ddr3, or lpddr2 devices up to 4 gb in density operating at up to 533 mhz ( 1066 mbps data rate). fpga configuration and processor booting the fpga fabric and hps in the soc fpga are powered independently. you can reduce the clock frequencies or gate the clocks to reduce dynamic power, or shut down the entire fpga fabric to reduce total system power. you can configure the fpga fabric and boot the hps independently, in any order, providing you with more design flexibility: ? you can boot the hps independently. after the hps is running, the hps can fully or partially reconfigure the fpga fabric at any time under software control. the hps can also configure other fpgas on the board through the fpga configuration controller. ? you can power up both the hps and the fpga fabric together, configure the fpga fabric first, and then boot the hps from memory accessible to the fpga fabric. although the fpga fabric and hps are on separate power domains, the hps must remain powered up during operation while the fpga fabric can be powered up or down as required. note: arria v device overview altera corporation av-51001 hpsCfpga axi bridges 32 2013.05.06 feedback
related information cyclone v device family pin connection guidelines provides detailed information about power supply pin connection guidelines and power regulator sharing. hardware and software development for hardware development, you can configure the hps and connect your soft logic in the fpga fabric to the hps interfaces using the qsys system integration tool in the quartus ii software. for software development, the arm-based soc fpga devices inherit the rich software development ecosystem available for the arm cortex-a9 mpcore processor. the software development process for altera soc fpgas follows the same steps as those for other soc devices from other manufacturers. support for linux, vxworks ? , and other operating systems will be available for the soc fpgas. for more information on the operating systems support availability, contact the altera sales team. you can begin device-specific firmware and software development on the altera soc fpga virtual target. the virtual target is a fast pc-based functional simulation of a target development systema model of a complete development board that runs on a pc. the virtual target enables the development of device-specific production software that can run unmodified on actual hardware. related information altera worldwide sales support dynamic and partial reconfiguration the arria v devices support dynamic reconfiguration and partial reconfiguration 25 . dynamic reconfiguration the dynamic reconfiguration feature allows you to dynamically change the transceiver data rates, pma settings, or protocols of a channel, without affecting data transfer on adjacent channels. this feature is ideal for applications that require on-the-fly multiprotocol or multirate support. you can reconfigure the pma, pcs, and pcie hard ip blocks with dynamic reconfiguration. partial reconfiguration partial reconfiguration is an advanced feature of the device family. if you are interested in using partial reconfiguration, contact altera for support. note: partial reconfiguration allows you to reconfigure part of the device while other sections of the device remain operational. this capability is important in systems with critical uptime requirements because it allows you to make updates or adjust functionality without disrupting services. apart from lowering cost and power consumption, partial reconfiguration increases the effective logic density of the device because placing device functions that do not operate simultaneously is not necessary. instead, you can store these functions in external memory and load them whenever the functions are required. this 25 partial reconfiguration is an advanced feature of the device family. if you are interested in using partial reconfiguration, contact altera for support. altera corporation arria v device overview 33 hardware and software development av-51001 2013.05.06 feedback
capability reduces the size of the device because it allows multiple applications on a single devicesaving the board space and reducing the power consumption. altera simplifies the time-intensive task of partial reconfiguration by building this capability on top of the proven incremental compile and design flow in the quartus ii design software. with the altera ? solution, you do not need to know all the intricate device architecture details to perform a partial reconfiguration. partial reconfiguration is supported through the fpp x16 configuration interface. you can seamlessly use partial reconfiguration in tandem with dynamic reconfiguration to enable simultaneous partial reconfiguration of both the device core and transceivers. enhanced configuration and configuration via protocol table 23: configuration modes and features of arria v devices arria v devices support 1.8 v , 2.5 v , 3.0 v , and 3.3 v 26 programming voltages and several configuration modes. remote system update partial reconfiguration 27 design se- curity decompression max data rate (mbps) max clock rate (mhz) data width mode yes yes yes 100 1 bit, 4 bits as through the epcs and epcq serial configuration device yes yes 125 125 1 bit ps through cpld or external microcontroller parallel flash loader yes yes 125 8 bits fpp yes 28 yes yes 125 16 bits yes yes 100 32 bits 29 yes yes yes x1, x2, x4, and x8 lanes cvp (pcie) 33 33 1 bit jtag parallel flash loader yes 28 yes yes 125 16 bits configuration via hps yes yes 100 32 bits instead of using an external flash or rom, you can configure the arria v devices through pcie using cvp. the cvp mode offers the fastest configuration rate and flexibility with the easy-to-use pcie hard ip block 26 arria v gz does not support 3.3 v . 27 partial reconfiguration is an advanced feature of the device family. if you are interested in using partial recon- figuration, contact altera for support. 28 supported at a clock rate of 50-62.5 mhz. 29 arria v gz only arria v device overview altera corporation av-51001 enhanced configuration and configuration via protocol 34 2013.05.06 feedback
interface. the arria v cvp implementation conforms to the pcie 100 ms power-up-to-active time requirement. although arria v gz devices support pcie gen3, you can use only pcie gen1 and pcie gen2 for cvp configuration scheme. note: related information configuration via protocol (cvp) implementation in altera fpgas user guide provides more information about cvp. power management leveraging the fpga architectural features, process technology advancements, and transceivers that are designed for power efficiency, the arria v devices consume less power than previous generation arria fpgas: ? total device core power consumptionless by up to 50%. ? transceiver channel power consumptionless by up to 50%. additionally, arria v devices contain several hard ip blocks, including pcie gen1 , gen2, and gen3, gbe, srio, gpon, and cpri protocols, that reduce logic resources and deliver substantial power savings of up to 25% less power than equivalent soft implementations. document revision history changes version date ? moved all links to the related information section of respective topics for easy reference. ? added link to the known document issues in the knowledge base. ? updated the available options, maximum resource counts, and per package information for the arria v sx and st device variants. ? updated the variable dsp multipliers counts for the arria v sx and st device variants. ? clarified that partial reconfiguration is an advanced feature. contact altera for support of the feature. ? added footnote to clarify that mlab 64 bits depth is available only for arria v gz devices. ? updated description about power-up sequence requirement for device migration to improve clarity. 2013.05.06 may 2013 ? added the l optional suffix to the arria v gz ordering code for the Ci3 speed grade. ? added a note about the power-up sequence requirement if you plan to migrate your design from the arria v gx a5 and a7, and arria v gt c7 devices to other arria v devices. 2013.01.11 january 2013 altera corporation arria v device overview 35 power management av-51001 2013.05.06 feedback
changes version date ? updated the summary of features. ? updated arria v gz information regarding 3.3 v i/o support. ? removed arria v gz engineering sample ordering code. ? updated the maximum resource counts for arria v gx and gz. ? updated arria v st ordering codes for transceiver count. ? updated transceiver counts for arria v st packages. ? added simplified floorplan diagrams for arria v gz , sx, and st. ? added fpp x32 configuration mode for arria v gz only. ? updated cvp (pcie) remote system update support information. ? added hps external memory performance information. ? updated template. 2012.11.19 november 2012 ? added arria v gz information. ? updated table 1, table 2, table 3, table 14, table 15, table 16, table 17, table 18, table 19, table 20, and table 21. ? added the arria v gz section. ? added table 8, table 9 and table 22. 3.0 october 2012 ? added Ci3 speed grade to figure 1 for arria v gx devices. ? updated the 6-gbps transceiver speed from 6.553 gbps to 6.5536 gbps in figure 3 and figure 1. 2.1 july 2012 ? restructured the document. ? added the embedded memory capacity and embedded memory configurations sections. ? added table 1, table 3, table 12, table 15, and table 16. ? updated table 2, table 4, table 5, table 6, table 7, table 8, table 9, table 10, table 11, table 13, table 14, and table 19. ? updated figure 1, figure 2, figure 3, figure 4, and figure 8. ? updated the fpga configuration and processor booting and hardware and software development sections. ? text edits throughout the document. 2.0 june 2012 ? updated table 1C7 and table 1C8. ? updated figure 1C9 and figure 1C10. ? minor text edits. 1.3 february 2012 minor text edits. 1.2 december 2011 arria v device overview altera corporation av-51001 document revision history 36 2013.05.06 feedback
changes version date ? updated table 1C1, table 1C2, table 1C3, table 1C4, table 1C6, table 1C7, table 1C9, and table 1C10. ? added soc fpga with hps section. ? updated clock networks and pll clock sources and ordering information sections. ? updated figure 1C5. ? added figure 1C6. ? minor text edits. 1.1 november 2011 initial release. 1.0 august 2011 altera corporation arria v device overview 37 document revision history av-51001 2013.05.06 feedback

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